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f OCnxPWM = -----------------------------------
ATmega128
The P W M frequency for the output can be calculated by the following equation:
f clk_I/O
N ? ( 1 + TOP )
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a P W M
waveform output in the fast P W M mode. If the OCRnx is set equal to BOTTOM (0x0000) the out-
put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast P W M mode can be achieved by set-
ting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only
if OCRnA is used to define the TOP value ( W GMn3:0 = 15). The waveform generated will have
a maximum frequency of f OC n A = f clk_I/O /2 when OCRnA is set to zero (0x0000). This feature is
similar to the OCnA toggle in CTC mode, except the double buffer feature of the output compare
unit is enabled in the fast P W M mode.
Phase Correct PWM
Mode
The phase correct Pulse Width Modulation or phase correct P W M mode ( W GMn3:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct P W M waveform generation option. The
R PCPWM = ----------------------------------
phase correct P W M mode is, like the phase and frequency correct P W M mode, based on a dual-
slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting compare output mode, the output compare (OCnx) is cleared
on the compare match between TCNTn and OCRnx while counting up, and set on the compare
match while downcounting. In inverting Output Compare mode, the operation is inverted. The
dual-slope operation has lower maximum operation frequency than single slope operation. How-
ever, due to the symmetric feature of the dual-slope P W M modes, these modes are preferred for
motor control applications.
The P W M resolution for the phase correct P W M mode can be fixed to 8-bit, 9-bit, or 10-bit, or
defined by either ICRn or OCRnA. The minimum resolution allowed is 2 bit (ICRn or OCRnA set
to 0x0003), and the maximum resolution is 16 bit (ICRn or OCRnA set to MAX). The P W M reso-
lution in bits can be calculated by using the following equation:
log ( 2 )
In phase correct P W M mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF ( W GMn3:0 = 1, 2, or 3), the value in ICRn
( W GMn3:0 = 10), or the value in OCRnA ( W GMn3:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct P W M mode is shown on Figure 53 . The figure
shows phase correct P W M mode when OCRnA or ICRn is used to define TOP. The TCNTn
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted P W M outputs. The small horizontal line marks on
the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx inter-
rupt flag will be set when a compare match occurs.
126
2467X–AVR–06/11
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